1. Technical Field
Embodiments of the present invention relate to a method of manufacturing an array substrate, and particularly to a method of manufacturing a plurality of array substrates by using a single substrate through a cutting process and an array substrate manufactured by the method.
2. Description of the Related Art
In prior arts, a liquid crystal panel of a display device mainly includes an array substrate, a color filter substrate arranged to be opposite to the array substrate and a liquid crystal layer between the color filter substrate and the array substrate. A method of manufacturing the array substrate mainly include the following steps: forming gate electrodes and gate lines electrically connected to the gate electrodes in a display region on a substrate, and forming common wires in a peripheral line region on the substrate; then, forming a gate electrode insulating layer by means of a plasma enhanced chemical vapor deposition (PECVD) process; forming an active layer on the gate electrode insulating layer; and forming a pattern of source electrodes and drain electrodes by means of a pattering process including an etching process.
In the above steps, during formation of the gate electrode insulating layer and an active layer by means of PECVD and formation of the pattern of the source electrodes and the drain electrodes by means of the pattering process including the etching process, since plasmas from a vacuum apparatus that performs PECVD process may not be ensured to be uniform and wirings designed in the array substrate are varied at different locations thereof, dense metal wires in the peripheral line region of the array substrate tends to occur abnormal arc discharge to burn out the gate lines and the data lines that are formed, causing failure of the final display panel product or break of the substrate and thus increasing failure ratio of product.
In an approach, arc discharge and burnout of the gate lines and data lines may be partially alleviated by adjusting line width of the test wires. However, in this approach, abnormal discharge will be caused on adjacent metal wires, which leads to failure of the product and fragment. Further, since the peripheral line region has a limited space for designing, adjustment of line width of the test lines and the common wires is limited, and thus abnormal discharge cannot be completely avoided.